Architectural Frameworks for Deterministic Cyber-Physical Systems: Integrating Component-Based Software Engineering, Multi-Core Resource Management, and Time-Sensitive Networking
Abstract
The rapid evolution of modern industrial and automotive systems has necessitated a paradigm shift from monolithic software designs to sophisticated, distributed component-based architectures. As these systems transition toward high-performance multi-core platforms and heterogeneous networking environments, ensuring temporal predictability and functional safety becomes increasingly complex. This research article provides a comprehensive investigation into the integration of component-based software models, such as the Rubus Component Model and COMDES-II, with advanced multi-core resource management techniques and deterministic communication standards. We explore the critical role of performance isolation in Multiprocessor Systems-on-Chip (MPSoC) through mechanisms like memory bandwidth reservation (MemGuard), cache partitioning (Coloris), and virtualization via real-time separation kernels. Furthermore, the article analyzes the shift from traditional Controller Area Networks (CAN) to Time-Sensitive Networking (TSN) and switched Ethernet, evaluating the timing analysis and modeling requirements for distributed vehicle functions. By synthesizing theoretical advancements in system-level performance analysis (SymTA/S) and fault-tolerant architectures, this study establishes a holistic framework for the design and optimization of next-generation cyber-physical systems. The findings emphasize the necessity of cross-layer predictability, from the software component level through the hypervisor and memory controller, to the network interface, ensuring that the rigorous demands of real-time control are met in the presence of task jitter and resource contention.
Keywords
Component-Based Software Engineering, Real-Time Systems, Multi-Core Resource Isolation, Time-Sensitive Networking
References
- Abdul Salam Abdul Karim. (2023). Fault-Tolerant Dual-Core Lockstep Architecture for Automotive Zonal Controllers Using NXP S32G Processors. International Journal of Intelligent Systems and Applications in Engineering, 11(11s), 877–885. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/7749
- Ashjaei, M., Mubeen, S., Lundbäck, J., Gålnander, M., Lundbäck, K., Nolte, T. Modeling and timing analysis of vehicle functions distributed over switched Ethernet. In: 43rd Annual Conference of the IEEE Industrial Electronics Society, 2017.
- Catalog of specialized CORBA specifications. OMG group, 2011.
- Farzaneh, M., Knoll, A. An ontology-based Plug-and-Play approach for in-vehicle Time-Sensitive Networking (TSN). 7th IEEE Annual Information Technology, Electronics and Mobile Communication Conference, IEMCON, pp. 1-8, 2016.
- Hänninen, K., et al. The rubus component model for resource constrained real-time systems. In: IEEE Symposium on Industrial Embedded Systems, 2008.
- Henia, R., Hamann, A., Jersak, M., Racu, R., Richter, K., Ernst, R. System level performance analysis - the SymTA/S approach. Comput. Digit. Tech., 152 (2), pp. 148-166, 2005.
- Ke, X., Sierszecki, K., Angelov, C. COMDES-II: A component-based framework for generative development of distributed real-time control systems. In: 13th International Conference on Embedded and Real-Time Computing Systems and Applications, 2007.
- Mubeen, S., Lawson, H., Lundbäck, J., Gålnander, M., Lundbäck, K. L. Provisioning of predictable embedded software in the vehicle industry: The rubus approach. In: IEEE/ACM 4th International Workshop on Software Engineering Research and Industrial Practice, SER&IP, pp. 3–9, 2017.
- Mubeen, S., Mäki-Turja, J., Sjödin, M. MPS-CAN analyzer: Integrated implementation of response-time analyses for Controller Area Network. J. Syst. Archit., 60 (10), pp. 828-841, 2014.
- Pop, P., Raagaard, M. L., Craciunas, S. S., Steiner, W. Design optimisation of cyber-physical distributed systems using IEEE time-sensitive networks. IET Cyber-Phys. Syst.: Theory Appl., 1 (1), pp. 86-94, 2016.
- Sentilles, S., Vulgarakis, A., Bures, T., Carlson, J., Crnkovic, I. A component model for control-intensive distributed embedded systems. In: International Conference on Component Based Software Engineering, CBSE, pp. 310–317, 2008.
- Tabish, R., Wen, J., Pellizzoni, R., et al. An analyzable inter-core communication framework for high-performance multicore embedded systems. Journal of Systems Architecture, p 10217, 2021.
- Toumassian, S., Werner, R., Sikora, A. Performance measurements for hypervisors on embedded arm processors. 2016.
- Tran, L., Radcliffe, P. J., Wang, L. Simulation is essential for embedded control systems with task jitter. Des. Autom. Embedded Syst., 25, pp. 177-191, 2021.
- Valsan, P. K., Yun, H. Medusa: A predictable and high-performance dram controller for multicore based embedded systems. In: 2015 IEEE 3rd International Conference on Cyber-Physical Systems, Networks, and Applications, pp 86–94, 2015.
- Venkata, S. K., Ahn, I., Jeon, D., et al. Sd-vbs: The san diego vision benchmark suite. In: IISWC. IEEE Computer Society, pp 55–64, 2009.
- Verbeek, F., Havle, O., Schmaltz, J., et al. Formal api specification of the pikeos separation kernel. NASA Formal Methods Symposium, Springer, pp. 375-389, 2015.
- West, R., Li, Y., Missimer, E., Danish, M. A virtualized separation kernel for mixed-criticality systems. ACM Trans. Comput. Syst. (TOCS), 34 (3), pp. 1-41, 2016.
- Wiki.Xenproject. Xen wiki - rtds-based-scheduler. 2019.
- WindRiver Systems Inc. Virtualization and the Internet of Things. WindRiver White Paper, p. 4, 2016.
- Wolf, W., Jerraya, A. A., Martin, G. Multiprocessor system-on-chip (MPSoC) technology. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 27 (10), pp. 1701-1713, 2008.
- Xi, S., Wilson, J., Lu, C., Gill, C. Rt-xen: Towards real-time hypervisor scheduling in xen. International Conference on Embedded Software, IEEE, pp. 39-48, 2011.
- Xilinx. ZCU 102 MPSoC TRM. 2022.
- Xilinx. Xilinx Versal. 2023.
- Xu, M. Rt-xen: Real-time virtualization based on xen. 2013.
- Ye, Y., West, R., Cheng, Z., Li, Y. Coloris: a dynamic cache partitioning system using page coloring. International Conference on Parallel Architecture and Compilation Techniques, IEEE, pp. 381-392, 2014.
- Yun, H., Ali, W., Gondi, S., et al. BWLOCK: a dynamic memory access control framework for soft real-time applications on multicore platforms. IEEE Trans Comput 66(7):1247–1252, 2017.
- Yun, H., Pellizzoni, R., Valsan, P. K. Parallelism-aware memory interference delay analysis for cots multicore systems. In: 2015 27th Euromicro Conference on Real-Time Systems, pp 184–194, 2015.
- Yun, H., Yao, G., Pellizzoni, R., Caccamo, M., Sha, L. Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. Real-Time and Embedded Technology and Applications Symposium, IEEE, pp. 55-64, 2013.
- Yun, H., Yao, G., Pellizzoni, R., et al. Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms. IEEE Transactions on Computers 65(2):562–576, 2016.