HARMONIZING HARDWARE AND ALGORITHMIC DESIGN: ADVANCES IN ENERGY-EFFICIENT ACCELERATORS FOR DEEP NEURAL NETWORKS AND LARGE-SCALE MACHINE LEARNING SYSTEMS

Abstract

The proliferation of deep learning has driven unprecedented demand for specialized computing architectures capable of delivering high throughput, low latency, and energy efficiency. While conventional general-purpose processors struggle to meet these requirements, accelerator-based solutions have emerged as a critical enabler for both research and deployment of large-scale neural networks. This article provides a comprehensive synthesis of recent developments in hardware accelerators for deep neural networks, encompassing convolutional neural networks, sparse architectures, and graph-based learning models, with a particular focus on energy-efficient designs, resilience strategies, and co-optimization of software and hardware. Theoretical frameworks and empirical findings are integrated to discuss the performance implications of low-voltage operation, in-memory computation, and compiler-level optimizations. Additionally, this work addresses the operational challenges of distributed model training, including network optimization, memory hierarchy, and the balance between latency and throughput. The discussion extends to neuromorphic computing and emerging paradigms that promise to reshape the landscape of artificial intelligence deployment. Finally, this paper examines the broader systemic implications of accelerator adoption, including environmental impact and resource allocation, and proposes future directions for the design of next-generation, energy-efficient, and resilient AI computing infrastructures.